Hybrid high-k dielectric material film stacks comprising zirconium oxide utilized in display devices

ABSTRACT

Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer comprising metal, and a gate electrode formed above or below the gate insulating layer

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims benefit of U.S. Provisional Application Ser. No.62/364,140 filed Jul. 19, 2016 (Attorney Docket No. APPM/24191L), whichis incorporated by reference in their entirety.

BACKGROUND Field

Embodiments of the present disclosure generally relate to forming ahybrid film stack having a high dielectric constant for display devices.More particularly, embodiments of the disclosure relate to methods forforming a hybrid film stack having a film layer with a high dielectricconstant fabricated by an atomic layer deposition (ALD) process withhigh film density and low film leakage for display applications.

Description of the Related Art

Display devices have been widely used for a wide range of electronicapplications, such as TV, monitors, mobile phone, MP3 players, e-bookreaders, and personal digital assistants (PDAs) and the like. Thedisplay device is generally designed for producing desired image byapplying an electric field to a liquid crystal that fills a gap betweentwo substrates (e.g., a pixel electrode and a common electrode) and hasanisotropic dielectric constant that controls the intensity of thedielectric field. By adjusting the amount of light transmitted throughthe substrates, the light and image intensity, quality and powerconsumption may be efficiently controlled.

A variety of different display devices, such as active matrix liquidcrystal display (AMLCD) or an active matrix organic light emittingdiodes (AMOLED), may be employed as light sources for display. In themanufacturing of display devices, an electronic device with highelectron mobility, low leakage current and high breakdown voltage, wouldallow more pixel area for light transmission and integration ofcircuitry, thereby resulting in a brighter display, higher overallelectrical efficiency, faster response time and higher resolutiondisplays. Low film qualities of the material layers, such as dielectriclayer with impurities or low film densities, formed in the device oftenresult in poor device electrical performance and short service life ofthe devices. Thus, a stable and reliable method for forming andintegrating film layers within TFT and OLED devices becomes crucial toprovide a device structure with low film leakage, and high breakdownvoltage, for use in manufacturing electronic devices with lowerthreshold voltage shift and improved the overall performance of theelectronic device are desired.

In particular, the interface management between a metal electrode layerand the nearby insulating materials becomes critical as impropermaterial selection of the interface between the metal electrode layerand the nearby insulating material may adversely result in undesiredelements diffusing into the adjacent materials, which may eventuallylead to current short, current leakage or device failure. Furthermore,the insulating materials with different higher dielectric constant oftenprovide different electrical performance, such as providing differentcapacitance in the device structures. Selection of the material of theinsulating materials not only affects the electrical performance of thedevice, incompatibility of the material of the insulating materials tothe electrodes may also result in film structure peeling, poor interfaceadhesion, or interface material diffusion, which may eventually lead todevice failure and low product yield.

In some devices, capacitors, e.g., a dielectric layer placed between toelectrodes, are often utilized and formed to store electric charges whenthe display devices are in operation. The capacitor as formed isrequired to have high capacitance for display devices. The capacitancemay be adjusted by changing of the dielectric material and dimension ofthe dielectric layer formed between the electrodes and/or thickness ofthe dielectric layer. For example, when the dielectric layer is replacedwith a material having a higher dielectric constant, the capacitance ofthe capacitor will increase as well. As the resolution requirement fordisplay devices is increasingly challenging, e.g., display resolutiongreater than 800 ppi, only limited areas are remained in the displaydevices to allow forming capacitors therein to increase electricalperformance. Thus, maintaining the capacitor formed in the displaydevices in a confined location with a relatively small area has becomecrucial.

Therefore, there is a need for improved methods for forming a dielectriclayer with high dielectric constant with desired film qualities and lowleakage for manufacturing display devices that produce improved deviceelectrical performance.

SUMMARY

Embodiments of the disclosure generally provide methods of forming ahybrid film stack that may be used as a capacitor layer or a gateinsulating layer with high dielectric constant as well as film qualitiesfor display applications. In one embodiment, a thin film transistorstructure include source and drain electrodes formed on a substrate, agate insulating layer formed on a substrate covering the source anddrain electrodes, wherein the gate insulating layer is hybrid film stackhaving a dielectric layer comprising a zirconium containing materialdisposed on an interface layer comprising metal, and a gate electrodeformed above or below the gate insulating layer.

In another embodiment, a method for forming a hybrid film stack fordisplay devices includes performing an interface layer comprisingaluminum of a hybrid film stack on a substrate, and performing adielectric layer of the hybrid film stack by an ALD process on theinterface layer, wherein the dielectric layer comprises zirconiumcontaining material, wherein the hybrid film stack is utilized as acapacitor layer or a gate insulating layer in display devices.

In yet another embodiment, a device structure utilized for displaydevices includes a hybrid film stack using as a capacitor structureformed between two electrodes in display devices, wherein the hybridfilm stack comprises an aluminum containing layer and a Zr containinglayer formed on the aluminum containing layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentdisclosure are attained and can be understood in detail, a moreparticular description of the disclosure, briefly summarized above, maybe had by reference to the embodiments thereof which are illustrated inthe appended drawings.

FIG. 1 depicts a sectional view of a processing chamber that may be usedto deposit a dielectric layer in accordance with one embodiment of thepresent disclosure;

FIG. 2 depicts a sectional view of a processing chamber that may be usedto deposit a dielectric layer in accordance with one embodiment of thepresent disclosure;

FIG. 3 is a schematic view of a multi-chamber substrate processingsystem including processing chambers described herein

FIG. 4 depicts a process flow diagram of one embodiment of a method offorming a hydride film stack with high capacitance on a substrate;

FIG. 5A-5C is a sectional view of one example of a hydride film stackwith high capacitance of FIG. 4 formed therein;

FIGS. 6A-6B are cross sectional view of different examples of a displaydevice structure with the hydride film stack with high capacitance ofFIG. 4 formed therein;

FIG. 7 is a sectional view of a capacitor structure formed in a displaydevice structure having a hydride film stack with high capacitance ofFIG. 4 formed therein; and

FIG. 8 is a sectional view of one example of a display device structurehaving a hydride film stack with high capacitance of FIG. 4 formedtherein.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements and features of oneembodiment may be beneficially incorporated in other embodiments withoutfurther recitation.

It is to be noted, however, that the appended drawings illustrate onlyexemplary embodiments of this disclosure and are therefore not to beconsidered limiting of its scope, for the disclosure may admit to otherequally effective embodiments.

DETAILED DESCRIPTION

Embodiments of the disclosure generally provide methods of forming ahybrid film stack having a high dielectric constant greater than 15 withenhanced electrical performance, such as high capacitance and lowleakage, with high dielectric constant for display devices. Suchdielectric layer with high dielectric constant may be formed as acapacitor, a gate insulating layer, or any suitable insulating materialsin display devices. The hybrid film stack having a high dielectricconstant may be formed by a combination of chemical vapor deposition(e.g., PECVD or MOCVD) process and an atomic layer deposition (ALD)process that may provide a film stack with low defect density, lowimpurities, low film leakage and high dielectric constant. The hybridfilm stack having a high dielectric constant may be utilized in anyinsulating structure and/or capacitor structures in TFT devices or OLEDdevices. In one example, the hybrid film stack with the high dielectricconstant may be used in any suitable layers, such as a gate insulatinglayer, a capacitor layer formed between two electrodes, aninter-insulating layer, an etching stop layer or an interface protectionlayer in display devices for electric performance enhancement andimprovement.

In some examples, the zirconium containing material as described in thisdisclosure may be exchanged or replaced with hafnium (Hf) containingmaterial, including hafnium oxide, doped hafnium, doped hafnium oxide orthe like.

FIG. 1 is a schematic cross-section view of one embodiment of a chemicalvapor deposition processing chamber 100 in which a dielectric layer,such as an insulating layer, a capacitor layer formed between twoelectrodes, a gate insulating layer, an etch stop layer, a passivationlayer, an interlayer insulator, a dielectric layer for capacitors orpassivation layer in display device structures, may be deposited. Onesuitable chemical vapor deposition chamber, such as plasma enhanced CVD(PECVD), is available from Applied Materials, Inc., located in SantaClara, Calif. It is contemplated that other deposition chambers,including those from other manufacturers, may be utilized to practicethe present disclosure.

The chamber 100 generally includes walls 142, a bottom 104 and a lid 112which bound a process volume 106. A gas distribution plate 110 andsubstrate support assembly 130 are disposed with in a process volume106. The process volume 106 is accessed through a valve 108 formedthrough the wall 142 such that a substrate 102 may be transferred in toand out of the chamber 100.

The substrate support assembly 130 includes a substrate receivingsurface 132 for supporting the substrate 102 thereon. A stem 134 couplesthe substrate support assembly 130 to a lift system 136 which raises andlowers the substrate support assembly 130 between substrate transfer andprocessing positions. A shadow frame 133 may be optionally placed overperiphery of the substrate 102 when processing to prevent deposition onthe edge of the substrate 102. Lift pins 138 are moveably disposedthrough the substrate support assembly 130 and are adapted to space thesubstrate 102 from the substrate receiving surface 132. The substratesupport assembly 130 may also include heating and/or cooling elements139 utilized to maintain the substrate support assembly 130 at a desiredtemperature. The substrate support assembly 130 may also includegrounding straps 131 to provide an RF return path around the peripheryof the substrate support assembly 130.

The gas distribution plate 110 is coupled at its periphery to a lid 112or wall 142 of the chamber 100 by a suspension 114. The gas distributionplate 110 may also be coupled to the lid 112 by one or more centersupports 116 to help prevent sag and/or control thestraightness/curvature of the gas distribution plate 110. The gasdistribution plate 110 may have different configurations with differentdimensions. In an exemplary embodiment, the gas distribution plate 110has a quadrilateral plan shape. The gas distribution plate 110 has adownstream surface 150 having a plurality of apertures 111 formedtherein facing an upper surface 118 of the substrate 102 disposed on thesubstrate support assembly 130. The apertures 111 may have differentshapes, number, densities, dimensions, and distributions across the gasdistribution plate 110. In one embodiment, a diameter of the apertures111 may be selected between about 0.01 inch and about 1 inch.

A gas source 120 is coupled to the lid 112 to provide gas through thelid 112 and then through the apertures 111 formed in the gasdistribution plate 110 to the process volume 106. A vacuum pump 109 iscoupled to the chamber 100 to maintain the gas in the process volume 106at a desired pressure.

An RF power source 122 is coupled to the lid 112 and/or to the gasdistribution plate 110 to provide a RF power that creates an electricfield between the gas distribution plate 110 and the substrate supportassembly 130 so that a plasma may be generated from the gases presentbetween the gas distribution plate 110 and the substrate supportassembly 130. The RF power may be applied at various RF frequencies. Forexample, RF power may be applied at a frequency between about 0.3 MHzand about 200 MHz. In one embodiment the RF power is provided at afrequency of 13.56 MHz.

In one embodiment, the edges of the downstream surface 150 of the gasdistribution plate 110 may be curved so that a spacing gradient isdefined between the edge and corners of the gas distribution plate 110and substrate receiving surface 132 and, consequently, between the gasdistribution plate 110 and the upper surface 118 of the substrate 102.The shape of the downstream surface 150 may be selected to meet specificprocess requirements. For example, the shape of the downstream surface150 may be convex, planar, concave or other suitable shape. Therefore,the edge to corner spacing gradient may be utilized to tune the filmproperty uniformity across the edge of the substrate, thereby correctingproperty non-uniformity in films disposed in the corner of thesubstrate. Additionally, the edge to center spacing may also becontrolled so that the film property distribution uniformity may becontrolled between the edge and center of the substrate. In oneembodiment, a concave curved edge of the gas distribution plate 110 maybe used so the center portion of the edge of the gas distribution plate110 is spaced farther from the upper surface 118 of the substrate 102than the corners of the gas distribution plate 110. In anotherembodiment, a convex curved edge of the gas distribution plate 110 maybe used so that the corners of the gas distribution plate 110 are spacedfarther than the edges of the gas distribution plate 110 from the uppersurface 118 of the substrate 102.

A remote plasma source 124, such as an inductively coupled remote plasmasource, may also be coupled between the gas source and the gasdistribution plate 110. Between processing substrates, a cleaning gasmay be energized in the remote plasma source 124 to remotely provideplasma utilized to clean chamber components. The cleaning gas enteringthe process volume 106 may be further excited by the RF power providedto the gas distribution plate 110 by the power source 122. Suitablecleaning gases include, but are not limited to, NF₃, F₂, and SF₆.

In one embodiment, the substrate 102 that may be processed in thechamber 100 may have a surface area of 10,000 cm² or more, such as25,000 cm² or more, for example about 55,000 cm² or more. It isunderstood that after processing the substrate may be cut to formsmaller other devices.

In one embodiment, the heating and/or cooling elements 139 may be set toprovide a substrate support assembly temperature during deposition ofabout 600 degrees Celsius or less, for example between about 100 degreesCelsius and about 500 degrees Celsius, or between about 200 degreesCelsius and about 500 degrees Celsius, such as about 300 degrees Celsiusand 500 degrees Celsius.

The nominal spacing during deposition between the upper surface 118 ofthe substrate 102 disposed on the substrate receiving surface 132 andthe gas distribution plate 110 may generally vary between 400 mil andabout 1,200 mil, such as between 400 mil and about 800 mil, or otherdistance required to obtain desired deposition results. In one exemplaryembodiment wherein the gas distribution plate 110 has a concavedownstream surface, the spacing between the center portion of the edgeof the gas distribution plate 110 and the substrate receiving surface132 is between about 400 mils and about 1400 mils, and the spacingbetween the corners of the gas distribution plate 110 and the substratereceiving surface 132 is between about 300 mils and about 1200 mils.

FIG. 2 is a schematic cross sectional view of an ALD (atomic layerdeposition) chamber 200 that may be used to perform a depositiondescribed herein. The ALD deposition process may be utilized to form adielectric layer, such as an insulating layer, a gate insulating layer,an etch stop layer, an interlayer insulator, a dielectric layer forcapacitor or passivation layer in display devices as described herein.The chamber 200 generally includes a chamber body 202, a lid assembly204, a substrate support assembly 206, and a process kit 250. The lidassembly 204 is disposed on the chamber body 202, and the substratesupport assembly 206 is at least partially disposed within the chamberbody 202. The chamber body 202 includes a slit valve opening 208 formedin a sidewall thereof to provide access to the interior of theprocessing chamber 200. In some embodiments, the chamber body 202includes one or more apertures that are in fluid communication with avacuum system (e.g., a vacuum pump). The apertures provide an egress forgases within the chamber 200. The vacuum system is controlled by aprocess controller to maintain a pressure within the ALD chamber 200suitable for ALD processes. The lid assembly 204 may include one or moredifferential pumps and purge assemblies 220. The differential pump andpurge assemblies 220 are mounted to the lid assembly 204 with bellows222. The bellows 222 allow the pump and purge assemblies 220 to movevertically with respect to the lid assembly 204 while still maintaininga seal against gas leaks. When the process kit 250 is raised into aprocessing position, a compliant first seal 286 and a compliant secondseal 288 on the process kit 250 are brought into contact with thedifferential pump and purge assemblies 220. The differential pump andpurge assemblies 220 are connected with a vacuum system (not shown) andmaintained at a low pressure.

As shown in FIG. 2, the lid assembly 204 includes a RF cathode 210 thatcan generate a plasma of reactive species within the chamber 200 and/orwithin the process kit 250. The RF cathode 210 may be heated by electricheating elements (not shown), for example, and cooled by circulation ofcooling fluids, for example. Any power source capable of activating thegases into reactive species and maintaining the plasma of reactivespecies may be used. For example, RF or microwave (MW) based powerdischarge techniques may be used. The activation may also be generatedby a thermally based technique, a gas breakdown technique, a highintensity light source (e.g., UV energy), or exposure to an x-raysource.

The substrate support assembly 206 can be at least partially disposedwithin the chamber body 202. The substrate support assembly 206 caninclude a substrate support member or susceptor 230 to support asubstrate 232 for processing within the chamber body. The susceptor 230may be coupled to a substrate lift mechanism (not shown) through a shaft224 or shafts 224 which extend through one or more openings 226 formedin a bottom surface of the chamber body 202. The substrate liftmechanism can be flexibly sealed to the chamber body 202 by a bellows228 that prevents vacuum leakage from around the shafts 224. Thesubstrate lift mechanism allows the susceptor 230 to be moved verticallywithin the ALD chamber 200 between a lower robot entry position, asshown, and processing, process kit transfer, and substrate transferpositions. In some embodiments, the substrate lift mechanism movesbetween fewer positions than those described.

In some embodiments, the substrate 232 may be secured to the susceptorusing a vacuum chuck (not shown), an electrostatic chuck (not shown), ora mechanical clamp (not shown). The temperature of the susceptor 230 maybe controlled (by, e.g., a process controller) during processing in theALD chamber 200 to influence temperature of the substrate 232 and theprocess kit 250 to improve performance of the ALD processing. Thesusceptor 230 may be heated by, for example, electric heating elements(not shown) within the susceptor 230. The temperature of the susceptor230 may be determined by pyrometers (not shown) in the chamber 200, forexample.

As shown in FIG. 2, the susceptor 230 can include one or more bores 234through the susceptor 230 to accommodate one or more lift pins 236. Eachlift pin 236 is mounted so that they may slide freely within a bore 234.The support assembly 206 is movable such that the upper surface of thelift pins 236 can be located above the substrate support surface 238 ofthe susceptor 230 when the support assembly 206 is in a lower position.Conversely, the upper surface of the lift pins 236 is located below theupper substrate support surface 238 of the susceptor 230 when thesupport assembly 206 is in a raised position. When contacting thechamber body 202, the lift pins 236 push against a lower surface of thesubstrate 232, lifting the substrate off the susceptor 230. Conversely,the susceptor 230 may raise the substrate 102 off of the lift pins 236.

In some embodiments, the susceptor 230 includes process kit insulationbuttons 237 that may include one or more compliant seals 239. Theprocess kit insulation buttons 237 may be used to carry the process kit250 on the susceptor 230. The one or more compliant seals 239 in theprocess kit insulation buttons 237 are compressed when the susceptorlifts the process kit 250 into the processing position.

FIG. 3 is a top plan view of a multi-chamber substrate processing system300 suitable for the fabrication of any suitable display devices, suchas organic light emitting diodes (OLEDS), thin-film transistors (TFT),thin-film encapsulation (TFE), and solar cell fabrication on flat media.The system 300 includes a plurality of processing chambers 100, 200, 340and one or more load lock chambers 305, 307 positioned around a centraltransfer chamber 315. The processing chambers 100, 200, 340 may beconfigured to complete a number of different processing steps to achievea desired processing of flat media, such as a large area substrate 102(outlined in dashed lines). The load lock chambers 305, 307 areconfigured to transfer a substrate in a quadrilateral form from anambient environment outside the multi-chamber substrate processingsystem 300 to a vacuum environment inside the transfer chamber 315.

Positioned within the transfer chamber 315 is a transfer robot 325having an end effector 330. The end effector 330 is configured to besupported and move independently of the transfer robot 325 to transferthe substrate 102. The end effector 330 includes a wrist 335 and aplurality of fingers 342 adapted to support the substrate 102. In oneembodiment, the transfer robot 325 is configured to be rotated about avertical axis and/or linearly driven in a vertical direction (Zdirection) while the end effector 330 is configured to move linearly ina horizontal direction (X and/or Y direction) independent of andrelative to the transfer robot 325. For example, the transfer robot 325raises and lowers the end effector 330 (Z direction) to variouselevations within the transfer chamber 315 to align the end effector 330with openings in the processing chambers 100, 200, 340 and the load lockchambers 305, 307. When the transfer robot 325 is at a suitableelevation, the end effector 330 is extended horizontally (X or Ydirection) to transfer and/or position the substrate 102 into and out ofany one of the processing chambers 100, 200, 340 and the load lockchambers 305, 307. Additionally, the transfer robot 325 may be rotatedto align the end effector 330 with other processing chambers 100, 200,340 and the load lock chambers 305, 307.

In one example, the processing chambers 100, 200, 340 incorporated inthe multi-chamber substrate processing system 300 may be the chemicalvapor deposition (PECVD or MOCVD) chamber 100 depicted in FIG. 1 and theatomic layer deposition (ALD) chamber 200 depicted in FIG. 2 or othersuitable chambers, such as HDP-CVD, MOCVD, PECVD, thermal CVD, thermalannealing, PVD, surface treatment, electron beam (e-beam) treatment,plasma treatment, etching chambers, ion implantation chambers, surfacecleaning chamber, metrology chambers, spin-coating chamber, polymerspinning deposition chamber or any suitable chambers as needed. In oneexample depicted in the multi-chamber substrate processing system 300,the system 300 includes the chemical vapor deposition (such as a PECVD)chamber 100, the atomic layer deposition (ALD) chamber 200 and othersuitable chambers 340 as needed. By such arrangement, the dielectriclayer formed by the ALD process and/or the PECVD process may also beintegrated to perform in a single chamber without breaking vacuum so asto maintain cleanliness of the substrate without undesired contaminationand residuals from the environment.

A portion of the interior of load lock chamber 305 has been removed toexpose a substrate support or susceptor 350 that is adapted to receiveand support the large area substrate 102 during processing. Thesusceptor 350 includes a plurality of lift pins 355 that are movablerelative to an upper surface of the susceptor 350 to facilitate transferof the large area substrate 102. In one example of a transfer process ofthe large area substrate 102, the lift pins 355 are extended away fromor above the upper surface of the susceptor 350. The end effector 330extends in the X direction into the processing chamber 100, 200, 340 orload lock chambers 305, 307 above the extended lift pins. The transferrobot 325 lowers the end effector 330 in the Z direction until the largearea substrate 102 is supported by the lift pins 355. The lift pins 355are spaced to allow the fingers 342 of the end effector 330 to pass thelift pins 355 without interference. The end effector 330 may be furtherlowered to assure clearance between the large area substrate 102 and thefingers 342 and the end effector 330 is retracted in the X directioninto the transfer chamber 315. The lift pins 355 may be retracted to aposition that is substantially flush with the upper surface of thesusceptor 350 in order to bring the large area substrate 102 intocontact with the susceptor 350 so the susceptor 350 supports the largearea substrate 102. A slit valve or door 360 between the transferchamber 315 and the load lock chamber 305, 307 (or the processingchamber or 100, 200, 340) may be sealed and processing may be commencedin the load lock chamber 305, 307 (or the processing chambers 100, 200,340). To remove the large area substrate 102 after processing, thetransfer process may be reversed, wherein the lift pins 355 raise thelarge area substrate 102 and the end effector 330 may retrieve the largearea substrate 102. In one example, the substrate 102 may be transferredinto the multi-chamber substrate processing system 300 through the firstload lock chamber 305. After the substrate 102 is oriented and alignedto a desired position, the substrate 102 is then transferred to any oneof the processing chambers 100, 200, 340 through the transfer chamber315 to perform any suitable processes as needed to form a devicestructure on the substrate 102. After the processes are completed in theprocessing chambers 100, 200, 340, then the substrate 102 is removedfrom and transferred out of the multi-chamber substrate processingsystem 300 from the second load lock chamber 307 as needed.

The environment in the substrate processing system 300 is isolated fromambient pressure (i.e. pressure outside the system 300) and ismaintained at a negative pressure by one or more vacuum pumps (notshown). During processing, the processing chambers 100, 200, 340 arepumped down to predetermined pressures configured to facilitate thinfilm deposition and other processes. Likewise, the transfer chamber 315is held at a reduced pressure during transfer of the large areasubstrates to facilitate a minimal pressure gradient between theprocessing chambers 100, 200, 340 and the transfer chamber 315. In oneembodiment, the pressure in the transfer chamber 315 is maintained at apressure lower than ambient pressure. For example, the pressure in thetransfer chamber may be about 7 Torr to about 10 Torr while the pressurein the processing chambers 100, 200, 340 may be lower. In oneembodiment, the maintained pressure within the transfer chamber 315 maybe substantially equal to the pressure within the processing chambers100, 200, 340 and/or load lock chambers 305 and 307 to facilitate asubstantially equalized pressure in the system 300.

During the transfer of the large area substrate 102 in the transferchamber 315 and the processing chambers 100, 200, 340, proper alignmentof the large area substrate 102 is crucial to prevent collisions and/ordamage of the large area substrate 102. Additionally, the interior ofthe system 300 must be kept clean and free from debris such as brokenpieces of a substrate, broken equipment, and other particulatecontamination. While some conventional systems include view windowsallowing line of sight viewing into the interior of the various chambers100, 200, 340, the windows may not allow a full view and/or preciseinspection of the large area substrates and the interior of the variouschambers 100, 200, 340. Also, the conventional systems are notconfigured to view the large area substrate 102 and provide a metric ofprocessing results while the large area substrates are in the system.

The transfer robot 325 includes one or more optical image sensors 365and 370 disposed on the transfer robot 325 as needed. The one or moreoptical image sensors 365, 370 may be optical scanners, imagers orcameras, such as a charged-coupled device (CCD), a complementary metaloxide semiconductor (CMOS) device, a video camera, and the like. In oneembodiment, one or more of the optical image sensors 365, 370 aremounted on the transfer robot 325 in a position to view the large areasubstrate 102, the fingers 342 and any object in the line of sight viewof the sensors 365, 370. In this embodiment, the image sensors 365, 370may be oriented to view objects substantially in the X and Y directionas well as the Z direction as the transfer robot 325 is stationary ormoving in the system 300. The image sensors 365, 370 may include wideangle optics, such as a fisheye lens, to enable a greater field of view.

FIG. 4 depicts a flow diagram of one embodiment of a process 400 forforming a hybrid film stack suitable for use in display devices, such asthin-film transistor devices or OLED devices. Such hybrid film stack maybe formed as a capacitor layer disposed between two metal layers to forma capacitor, or an insulating layer in display devices. Suitableexamples of the insulating layer used in display devices include a gateinsulating layer, a capacitor layer disposed between two metal layers,an interface layer, a dielectric layer utilized to form a capacitor, anetch stop layer or a passivation layer where an insulating material isneeded. The insulating layer may be formed by a plasma enhanced chemicalvapor deposition (PECVD) process, which may be practiced in theprocessing chamber 100, as described in FIG. 1, and/or an atomic layerdeposition (ALD) process, which may be practiced in the processingchamber 200, as described in FIG. 2, or other suitable processingchamber, or in combination thereof.

The process 400 begins at operation 402 by providing the substrate 102in a processing chamber, such as the processing chamber 100 (a PECVDchamber) or processing chamber 200 (an ALD chamber) depicted in FIG. 3,to form an insulating layer or a dielectric layer. The substrate 102 mayhave different combinations of films, structures or layers previouslyformed thereon to facilitate forming different device structures ordifferent film stacks on the substrate 102. The substrate 102 may be anyone of glass substrate, plastic substrate, polymer substrate, metalsubstrate, singled substrate, roll-to-roll substrate, or other suitabletransparent substrate suitable for forming a thin film transistorthereon.

At operation 402, a deposition process is then performed on thesubstrate 102 to form a first layer 504 of a hybrid film stack 510(depicted in FIG. 5C) on the substrate 102. In one example, theresultant hybrid film stack 510 may be formed as a gate insulating layeror a capacitor layer in display devices. In such example, the resultanthybrid film stack 510 of the gate insulating layer and/or the capacitorlayer in display devices may be in form of multiple layers, which willbe described later with reference to FIGS. 5B and 5C.

The first layer 504 is formed on a surface 501 of the substrate 102 by aplasma enhanced chemical vapor deposition (PECVD) process. The firstlayer 504 is a dielectric layer, such as a silicon containing layer.Suitable examples of the silicon containing layer may include siliconoxide, silicon oxynitride, silicon carbide, silicon oxycarbide orsilicon nitride, formed by the CVD process. As silicon materials arewidely used in display devices, the first layer 504 referred here couldbe any existing materials come with the substrate pre-formed in thedisplay devices prior to a second layer 508 (depicted in FIG. 5B) to beformed thereon. In one example, the first layer 504 is a silicon nitrideor a silicon oxide material.

In one example wherein the substrate 102 already includes a siliconcontaining material pre-fabricated thereon, the first layer 504 may beeliminated and the process 400 for forming the hybrid film stack 510 maybe directly start from operation 406 to form the interface layer 506.

At operation 406, an interface layer 506 is formed on the first layer504, as shown in FIG. 5B. As the second layer 508 (shown in FIG. 5C)formed thereon is a dielectric layer with high dielectric constant thatincludes certain metal elements, direct contact of the elements (e.g.,metal elements or oxygen elements) from the second layer 508 with thesilicon elements from the first layer 504 often result in interfacediffusion, which may result in a undesired diffusion layer formed at theinterface. The elements (e.g., metal elements or oxygen elements) fromthe second layer 508 diffused and penetrated into the first layer 504forms impurities at the interface deteriorating the film qualities ofboth first and second layers 504, 508 and eventually leading to deviceshort, current leakage or device failure, that adversely shorten thelifetime of the device structure. Thus, by forming the interface layer506 between the first layer 504 and the second layer 508, the secondlayer 508 is then interfaced with the interface layer 506, which is moreinert to the film properties from both the first and the second layer504, 508, rather than in direct contact with the first layer 504 so thatgood interface control may be obtained.

In one example, the interface layer 506 is metal dielectric layer formedby a plasma enhanced chemical deposition process, such as the processingchamber 100 depicted in FIG. 1, or an atomic layer deposition processingchamber 200 (or a PE-ALD processing chamber) depicted in FIG. 2. In oneexample, the interface layer 506 may be an aluminum containing material,such as aluminum oxide (Al₂O₃), aluminum nitride (AlN), titanium oxide(TiO₂), aluminum titanium oxide (AlTiO), aluminum zirconium oxide(AlZrO), zinc oxide (ZnO), indium tin oxide (ITO), AlON, or othersuitable metal dielectric layer materials. Zinc oxide (ZnO) or indiumtin oxide (ITO) may also be utilized to form the interface layer. In oneparticular example, the interface layer 506 is an aluminum oxide (Al₂O₃)or aluminum nitride (AlN) layer.

The ALD process is enabled by a slow deposition process with a firstmonolayer of atoms being absorbed and adhered on a second monolayer ofatoms formed on a substrate surface. Strong adherence of atoms in eachlayers and absorbability of the layers of atoms onto the surface ofsubstrate provide compact and secured bonding structures in the filmstructures so as to render a film property with a high film density(compared to a chemical vapor deposition process) that may efficientlyprevent moisture or contaminant from penetrating therethrough.Furthermore, the slow ALD deposition rate of the interface layer 506also allows the atoms from the interface layer 506 to gradually fill inthe pinholes, pores, pits or defects that may be occurred from thesubstrate surface (e.g., the first layer 504 in the examples of FIG. 5B)so as to assist repairing the film defects from the substrate surface.In contrast, the conventional plasma enhanced chemical vapor depositionprocess (PECVD) often provides a relatively fast deposition process withhigh throughput but renders relatively porous film structures for theresultant film layer. The interface layer 506 serves as abarrier/blocking layer to prevent elements from the first and the secondlayers 504, 508 to penetrate or diffuse therethrough to undesirablyalter the device performance. In the example wherein high throughput ofthe manufacturing cycles is desired, a plasma assisted atomic layerdeposition (PE-ALD) process may be utilized instead to provide arelatively higher deposition rate (compared to thermal ALD) ofdeposition process while still maintaining the desired degree of filmdensity. In some embodiment wherein even higher throughput of themanufacturing cycles is desired, the interface layer 506 may beconfigured to formed by a CVD process while the second layer 508, a highdielectric constant greater than 15, subsequently formed thereon is thenformed by an ALD process to ensure the particular film properties, e.g.,high film density and low defect density, is achieved for the overallhybrid film stack 510.

In one example, the precursors used in the ALD process for forming theinterface layer 506 as a Al₂O₃ layer includes at least a metalcontaining precursor, such as an aluminum containing gas, and a reactinggas. Suitable examples of the aluminum containing gas may have a formulaof R_(x)Al_(y)R′_(z)R″_(v) or R_(x)Al_(y)(OR′)_(z), where R, R′ and R″are H, CH₃, C₂H₅, C₃H₇, CO, NCO, alkyl or aryl group and x, y, z and vare integers having a range between 1 and 8. In another embodiment, thealuminum containing compound may have a formula of Al(NRR′)₃, where Rand R′ may be H, CH₃, C₂H₅, C₃H₇, CO, NCO, alkyl or aryl group and R′may be H, CH₃, C₂H₅, C₃H₇, CO, NCO, alkyl or aryl group. Examples ofsuitable aluminum containing compounds are diethylalumium ethoxide(Et₂AlOEt), triethyl-tri-sec-butoxy dialumium (Et₃Al₂OBu₃, or EBDA),trimethylaluminum (TMA), trimethyldialumium ethoxide, dimethyl aluminumisupropoxide, disecbutoxy aluminum ethoxide, (OR)₂AlR′, wherein R, R′and R″ may be methyl, ethyl, propyl, isopropyl, butyl, isobutyl,tertiary butyl, and other alkyl groups having higher numbers of carbonatoms, and the like.

The reacting gas that may be supplied to form aluminum containingmaterial gas includes an oxygen containing gas, such as, oxygen (O₂),ozone (O₃), nitrogen (N₂), N₂O, CO₂, NO, CO, CO₂ and among others.

In one example, the interface layer may have a thickness of betweenabout 1.5 Å and about 30 Å, such as about 10 Å.

At operation 408, after the interface layer 506 is formed on the firstlayer 504, the second layer 508 is then formed on the interface layer506. The second layer 508 is formed by the atomic layer depositionprocess comprising Zr containing material. In one example, the secondlayer 508 is a Zr containing material, such as zirconium oxide (ZrO₂),formed in cubic or tetragonal structures, providing the second layer 508with high dielectric constant greater than 25. A ZrO₂ layer formed by anatomic layer deposition process often predominately provides theresultant ZrO₂ in crystalline structure in cubic or tetragonal phase,providing a dielectric constant at least greater than 25, such asbetween about 25 and about 50. The Zr containing layer formed as thesecond layer 508 of the hybrid film stack 510 by an atomic layerdeposition (ALD) process may provide good film properties, such as highthermal stability, high deposition rate, high film density, low defectdensity and the like as well as the desired high dielectric constant.

In one example, the precursor mixtures utilized to form the second layer508 include alternatively or sequentially supplying a zirconiumcontaining precursor with or without the reactive gaseous species toform an aluminum doped zirconium (Zr) containing layer. Suitablezirconium containing precursor include Zr-organometallic precursors,such as tetrakis(ethylmethylamino)zirconium (TEMAZ),tris(dimethylamino)cyclopentadienyl zirconium (C₅H₅)Zr[N(CH₃)₂]₃, or thelike. In one particular example utilized herein, the zirconiumcontaining precursor is tetrakis(ethylmethylamino)zirconium (TEMAZ). Thereactive gaseous species may be oxygen containing gases, such as H₂O,O₂, O₃, H₂O₂, CO₂, NO₂, N₂O, and the like. In one example, the oxygencontaining gas is O₂ or O₃.

In one example, the second layer 508 of the hybrid film stack 510 asformed may have a dielectric constant greater than 25, such as between25 and 50. In one example, the second layer 508 of the hybrid film stack510 has a thickness between about 3 Å and about 500 Å.

In some examples, the Zr containing layer formed in the second layer 508may have dopants doped therein to keep a current leakage at a desiredlow level. As the dielectric constant of a material increases, the bandgap of the material decreases, leading to high leakage current in thedevice. Thus, higher dielectric constant, e.g., greater than 25, of adielectric layer is desired for the advanced technologies so as toprovide a capacitor with higher capacitance. In contrast, higherdielectric constant, e.g., greater than 25, of the dielectric layer alsooften results in high film leakage that may eventually lead to devicefailure. Thus, by providing dopants, such as the aluminum dopants, intothe Zr containing layer in the second layer 508, the crystallinestructure of the Zr containing layer in the second layer 508 may bealtered into an amorphous state, thus lowering the dielectric constantof a certain predetermined level so as to keep the current leakage at adesired low level. For example, by providing aluminum dopant into theZrO₂ structure to form the second layer 508 may render the resultantZrO₂ structure in amorphous state, thus, keeping the dielectric constantof the amorphous aluminum doped ZrO₂ at a desired range less than 25 butstill above 15, such as between about 15 and 25. Alternatively, thesecond layer 508 may be formed including both amorphous and crystallinestructures, such as a portion of the ZrO₂ layer with dopants and anotherportion without dopants (e.g., a hybrid bonding structure), so as toobtain the resultant hydride film stack 510 with desired dielectricconstant level, as well as desired low leakage level and good interfacecontrol.

In the example wherein the doped ZrO₂ layer is used for the second layer508, the doped ZrO₂ layer dielectric constant greater than 15, such asbetween 15 and 25 and a film leakage about 1 E-8 A/cm² or below. Thealuminum dopant in a ZrO₂ structure may have a doping concentrationbetween about 10 atm. % and about 20 atm. %.

It is noted that the first layer 504, the interface layer 506 and thesecond layer 508 of the hybrid film stack 510 may be all formed in thesame processing system, such as the processing system 300 depicted inFIG. 3 without breaking vacuum. For example, the first layer 504 may beformed in the processing 100 integrated in the processing system 300.The interface layer 506 may be formed in the processing chamber 100 orprocessing chamber 200 integrated in the processing system 300 while thesecond layer 508 may be formed in the processing chamber 200 allintegrated in the processing system 300 as needed to save manufacturingcycling time as well as maintaining low substrate contaminant as needed.

FIG. 6A depicts an example of a TFT device structure 650 utilizing thehybrid film stack 510 in the TFT device structure 650 to form acapacitor, or a gate insulating layer, or other suitable insulatinglayers. A portion of the exemplary TFT device structure 650 is depictedin FIG. 6A formed on the substrate 102. The TFT device structure 650comprises a low temperature polysilicon (LTPS) TFT for OLED device. TheLTPS TFT device structures 650 are MOS devices built with a sourceregion 609 a, channel region 608, and drain region 609 b formed on theoptically transparent substrate 102 with or without an optionalinsulating layer 604 disposed thereon. The source region 609 a, channelregion 608, and drain region 609 b are generally formed from aninitially deposited amorphous silicon (a-Si) layer that is typicallylater thermal or laser processed to form a polysilicon layer. Thesource, drain and channel regions 609 a, 608, 609 b can be formed bypatterning areas on the optically transparent substrate 102 and iondoping the deposited initial a-Si layer, which is then thermally orlaser processed (e.g., an Excimer Laser Annealing process) to form thepolysilicon layer. A gate insulating layer 605 (e.g., the insulatinglayer or the hybrid film stack 510 with high dielectric constant formedby the process 400 of FIG. 4) may be then deposited on top of thedeposited polysilicon layer(s) to isolate a gate electrode 614 from thechannel region 608, source region 609 a and drain regions 609 b. Thegate electrode 614 is formed on top of the gate insulating layer 605.The gate insulating layer 605 is also commonly known as a gate oxidelayer. A capacitor layer 612 (e.g., may also be the insulating layer orthe hybrid film stack 510 formed by the process 400 of FIG. 4) anddevice connections are then made through the insulating material toallow control of the TFT device. As indicated by the circles in FIG. 6A,the gate insulating layer 605 and the capacitor layer 612 in the TFTdevice structure 650 may also be fabricated by the hybrid film stack 510with high dielectric constant as well as the low film leakage includingthe first layer 504 and the second layer 508 and the interface layer 506formed therebetween. In the embodiment wherein the optional insulatinglayer 604 is present, the first layer 504 comprising the siliconcontaining layer may be eliminated as the insulating layer 604 and thefirst layer 504 may both be formed from a silicon material.

The TFT device structure 650 of FIG. 6A is just partially formed forease of description and explanation regarding to where the hybrid filmstack 510 may be utilized in some locations in the device structure 650utilized to form either the gate insulating layer 605 or the capacitorlayer 612, or both, in the device structure 650.

After the capacitor layer 612 is formed, an interlayer insulator 606 maybe formed on the capacitor layer 612. The interlayer insulator 606 maybe any suitable dielectric layer, such as silicon oxide or siliconnitride materials. The interlayer insulator 606 may be in form of asingle layer formed on the capacitor layer 612. Alternatively, theinterlayer insulator 606 may be in form of multiple layers as needed fordifferent device requirements. In the example depicted in FIG. 6A, theinterlayer insulator 606 includes a first dielectric layer 602 ofsilicon nitride formed on a second layer 603 of a silicon oxide layer.Subsequently, a source-drain metal electrode layer 610 a, 610 b is thendeposited, formed and patterned in the interlayer insulator 606, thecapacitor layer 612 and the gate insulating layer 605 electricallyconnected to the source region 609 a and drain regions 609 b.

After the source-drain metal electrode layer 610 a, 610 b is patterned,the planarization layer 615 is then formed over the source-drain metalelectrode layer 610 a, 610 b. The planarization layer 615 may befabricated from polyimide, benzocyclobutene-series resin, spin on glass(SOG) or acrylate. The planarization layer 615 is later patterned toallow a pixel electrode 616 to be formed on and filled in theplanarization layer 615, electrically connecting to the source-drainmetal electrode layer 610 a, 610 b.

In this example depicted in FIG. 5A, the capacitor layer 612 is formedon the gate electrode 614 extending to a capacitor structure 613 (e.g.,a MIM (metal-insulating-metal) structure) formed between an upperelectrode 611 and a lower electrode 609. The upper electrode 611 may belaterally coupled to the source-drain metal electrode layer 610 a, 610 bwhile the lower electrode 609 may be laterally coupled to the gateelectrode 614, or other suitable electrodes in the device structure 650.The capacitor structure 613 formed in the device structure 650 may be astorage capacitor that may improve the display device electricalperformance. It is noted that the capacitor structure 613 may be formedin any location suitable in the device structure 650 as needed fordifferent device performance requirements.

In another example depicted in FIG. 6B, a capacitor structure 622,similar to the capacitor structure 613 depicted in FIG. 6A, may beformed with different dimensions and/or profiles of the hybrid filmstack 510 severing as a capacitor layer 620 formed between the upperelectrode 611 and the lower electrode 609. Unlike the capacitor layer612 shown in FIG. 6A that extends from the area above the gate electrode614 to the area between the upper and the lower electrode 611, 609, thecapacitor layer 620 depicted in FIG. 6B is formed substantially in thearea between the upper and the lower electrodes 611, 609. Thus, aregular interlayer insulator 624 comprising silicon oxide or siliconoxide may be formed on the gate insulting layer 605 surrounding thecapacitor structure 622. The hybrid film stack 510 formed as thecapacitor layer 620 in the capacitor structure 622 may have a bottomsurface in contact with the lower gate insulating layer 605 as needed.The interlayer insulator 624 may be in a single layer form, as depictedin FIG. 6B, or in multiple layer form as needed.

It is noted that the hybrid film stack 510 formed by the process 400 maybe utilized to form the capacitor layer 620, gate insulating layer 605,as indicated in the circles of FIG. 6B, a passivation layer or any othersuitable layers that require insulating materials in the TFT devicestructures 650 including LTPS TFT for LCD or OLED TFT as needed.

It is noted that the upper electrode 611 and the lower electrode 609utilized to form the capacitor structures 622, 613 may also be pixelelectrodes and/or common electrodes as needed.

FIG. 7 depicts a simple capacitor structure 702 (e.g., a MIM(metal-insulating-metal) structure) that may be formed on the substrate102 utilized in display devices. Similar the upper electrode 611 and thelower electrode 609, (or a pixel electrode and a common electrode in aTFT device structure), the capacitor structure 702 includes a topelectrode 704 and a bottom electrode 708 having the hybrid film stack510 as a capacitor layer disposed in between to form the capacitorstructure 702. The capacitor layer comprises a high-k materialcomprising ZrO₂ with or without aluminum dopants and an aluminum oxidelayer as an interface layer. The hybrid film stack 510 serving as acapacitor layer in a capacitor structure may also in form of any numbersof the layers as needed.

FIG. 8 depicts yet another example of a TFT device structure 850.Similar to the structure described above, the TFT device structure 850includes a regular interlayer insulator 820 disposed on the gateelectrode 614. A passivation layer 822 may be formed on the interlayerinsulator 820. Another portion of the source and drain region 902(electrically connected to the source and drain region 609 a, 609 b) isshown on the optional insulating layer 604. Another portion of thesource-drain metal electrode layer 810 (electrically connected to thesource-drain metal electrode layer 610 a, 610 b) is disposed on andelectrically coupled to the source and drain region 902. A pixelelectrode 808 may be electrically connected to the source-drain metalelectrode layer 810, 610 a, 610 b. In this particular example, a portionof a gate insulating layer 605 passes through and between the gateelectrode 614 and the channel region 608, extending to the area abovethe source and drain region 902. In one example, the gate insulatinglayer 605 may be the hybrid film stack 510 formed using the process 400described above with referenced to FIG. 4. An additional electrode 804is formed above the source and drain region 802 and the gate insulatinglayer 605, forming a capacitor structure 806 in the device structure850. The additional electrode 804 formed on the gate insulating layer605 (now also serves as a capacitor layer) may be electrically connectedto the gate electrode 614. Thus, the additional electrode 804 and thesource and drain region 902 along with the gate insulating layer 605formed therebetween form the capacitor structure 806 in the devicestructure 850. Similarly, the gate insulating layer 605, now also servesas a capacitor layer, may be similar to the capacitor layer 612described above and may be in form of any of the layers as needed.

It is noted that the source-drain metal electrode layer 610 a, 610 b,810, the pixel electrode 808, the common electrode, the gate electrode614, the upper electrode 611, the lower electrode 609, the top electrode704, the bottom electrode 708, additional electrode 804 and anyelectrodes in the device structures may be any suitable metallicmaterials, including transparent conductive oxide layer (such as ITO orthe like), silver nano ink, carbon nano tube(CNT), silver nano ink andCNT, graphene, aluminum (Al), tungsten (W), chromium (Cr), tantalum(Ta), molybdenum (Mo), copper (Cu), TiN, MoO₂, MoN_(x), combinationthereof or any suitable materials.

It is noted that the structures above the passivation layer 822 or theplanarization layer 615 are eliminated for sake of brevity. However, insome exemplary device structures, an additional OLED or LCD devices, orother suitable devices may be formed above the passivation layer 822 orthe planarization layer 615 to form other suitable flexible mobiledisplay devices, such as LTPS OLED display devices with touch screenpanels as needed.

Thus, the methods described herein advantageously improve the electronstability, electrical performance, low leakage and good film stackintegration of display device structures by controlling the materials,particular a hybrid film stack having a high-k material comprising Zrcontaining layer formed on an interface layer comprising aluminumcontaining layer. The hybrid film stack may be fabricated either an ALDor PE-ALD and/or PECVD process, and structures of a gate insulatinglayer, capacitor layer, interlayer insulator, passivation layer,insulating materials in the display devices, along with a dielectriclayer formed as a capacitor in the display devices with desired highelectrical performance.

While the foregoing is directed to embodiments of the presentdisclosure, other and further embodiments of the disclosure may bedevised without departing from the basic scope thereof, and the scopethereof is determined by the claims that follow.

What is claimed is:
 1. A thin film transistor structure comprising:source and drain electrodes formed on a substrate; a gate insulatinglayer formed on a substrate covering the source and drain electrodes,wherein the gate insulating layer is hybrid film stack having adielectric layer comprising a zirconium containing material disposed onan interface layer comprising metal; and a gate electrode formed aboveor below the gate insulating layer.
 2. The structure of claim 1, furthercomprising: a capacitor layer formed on the gate electrode, wherein thecapacitor layer is a hybrid film stack having a dielectric constantgreater than
 15. 3. The structure of claim 1, wherein the hybrid filmstack has a dielectric constant greater than
 15. 4. The structure ofclaim 1, wherein the interface layer is at least one of aluminum oxide(Al₂O₃), aluminum nitride (AlN), titanium oxide (TiO₂), aluminumtitanium oxide (AlTiO), aluminum zirconium oxide (AlZrO), zinc oxide(ZnO), indium tin oxide (ITO) or AlON.
 5. The structure of claim 1,wherein the interface layer of the hybrid film is formed on a siliconcontaining material.
 6. The structure of claim 1, wherein the dielectriclayer comprising the zirconium containing material comprises aluminum inan amorphous structure.
 7. The structure of claim 1, wherein thedielectric layer comprising the zirconium containing layer has acrystalline structure.
 8. The structure of claim 6, wherein thedielectric layer is an aluminum doped ZrO₂ layer having a dielectricconstant between about 15 and
 25. 9. The structure of claim 7, whereinthe dielectric layer is a ZrO₂ layer having a dielectric constantbetween about 25 and about
 50. 10. The structure of claim 1, wherein thedielectric layer or the interface layer is formed by a ALD process or aPE-ALD process.
 11. The structure of claim 6, where the first layer ofthe zirconium containing material comprising aluminum has an aluminumconcentration between about 10 atm. % and about 20 atm. %.
 12. Thestructure of claim 5, wherein the silicon containing material is siliconoxide or silicon nitride.
 13. A method for forming a hybrid film stackfor display devices, comprising: performing an interface layercomprising metal of a hybrid film stack on a substrate; and performing adielectric layer of the hybrid film stack by an ALD process on theinterface layer, wherein the dielectric layer comprises zirconiumcontaining material, wherein the hybrid film stack is utilized as acapacitor layer or a gate insulating layer in display devices.
 14. Themethod of claim 13, wherein the substrate comprising silicon materialfurther comprises: a silicon material disposed on the substrate.
 15. Themethod of claim 13, wherein the dielectric layer comprising thezirconium containing material comprises aluminum in an amorphousstructure.
 16. The method of claim 13, wherein the dielectric layercomprising the zirconium containing material has a crystallinestructure.
 17. The method of claim 15, wherein the interface layer is atleast one of aluminum oxide (Al₂O₃), aluminum nitride (AlN), titaniumoxide (TiO₂), aluminum titanium oxide (AlTiO), aluminum zirconium oxide(AlZrO), zinc oxide (ZnO), indium tin oxide (ITO) or AlON.
 18. Thestructure of claim 16, wherein the dielectric layer is a ZrO₂ layerhaving a dielectric constant between about 25 and about
 50. 19. A devicestructure utilized for display devices, comprising: a hybrid film stackusing as a capacitor structure formed between two electrodes in displaydevices, wherein the hybrid film stack comprises an aluminum containinglayer and a Zr containing layer formed on the aluminum containing layer.20. The device structure of claim 19, further comprising: a siliconcontaining layer in the hybrid film stack formed under the aluminumcontaining layer.